Why does the Intel® Arria® 10 FPGA PCIe Hard IP fail to set the pattern lock bit when receiving a modified compliance pattern during the LTSSM=Polling Compliance state?

Description

According to PCIe specification, when a PCIe RootPort or EndPoint is in the LTSSM polling compliance state, it should set the pattern lock bit in data transmitted when it receives the modified compliance pattern and locks to the pattern.

Due to a bug in the Intel® Arria® 10 FPGA PCIe Hard IP, it will never lock to the modified compliance pattern.  The Intel® Arria® 10 FPGA PCIe Hard IP requires the data pattern 4a_bc_b5_bc {K28.5, D10.2, K28.5, D21.5 } to be one of the following sequence:

1. bc_4a_b5_bc {K28.5, D10.2, D21.5, K28.5 }
2. bc_bc_4a_b5 {K28.5, K28.5, D10.2, D21.5 }
3. b5_bc_bc_4a {D21.5, K28.5, K28.5, D10.2 }
4. 4a_b5_bc_bc {D10.2, D21.5, K28.5, K28.5 }

Resolution

No workaround for this problem exists. The user application should be aware of the limitation and take care of this scenarios.

This problem will not be fixed in a future release of the Intel® Quartus® Prime Software.