Why does the GTS SDI II IP Multi-rate Serial Loopback Design Example fail to achieve lock on Agilex™ 5 FPGA E-Series Modular Development Kit at 12G data rate?

Description

Due to a problem in the Quartus® Prime Pro Edition software version 25.3, you may observe the rx_align, rx_frame and rx_trs signals fail to achieve lock when running the GTS SDI II IP Multi-rate Serial Loopback Design Example on Agilex™ 5 FPGA E-Series Modular Development Kit at 12G data rate. 

Resolution

There is no workaround. This problem will be fixed in a future release of the Quartus® Prime Pro Edition Software.