Why does the bandwidth setting not change when using the fPLL Intel® Arria® 10/Cyclone® 10 FPGA IP in SDI_Direct mode?

Description

When using the fPLL Intel® Arria® 10/Cyclone® 10 FPGA IP in SDI_Direct mode, the bandwidth setting is fixed to an optimal configuration. Hence changes to the bandwidth setting (Low, Medium, High) in this IP will not be applied to the generated MIF file.

Resolution

This is expected behavior.