Why does the Avalon®-MM Intel® Stratix® 10 Hard IP for PCI* Express IP's dynamically generated design example fail timing on Intel® Stratix® 10 ES1 and ES2 devices?

Description

Due to a problem with the Intel® Quartus® Prime Pro Ediiton Software version 18.0 and 18.1, the Avalon®-MM Intel® Stratix® 10 Hard IP for PCI Express IP's dynamic generated design example fails static timing analysis.

Resolution

This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 18.1.1.