Why does the Agilex® 5 FPGA E-Series 065B Modular Development Kit 10GbE System Example Design fail to boot from the SD card with "Card did not respond to voltage select"?

Description

Due to a problem in the Agilex® 5 Ethernet System Example Design (SED) for the Agilex® 5 FPGA and SoC E-Series 065B Modular Development Kit (MDK, ordering code MK-A5E065BB32AEA), designed with the Quartus® Prime Pro Edition Software version 26.1 (SED release Q26.1 Rel-1.2), the Hard Processor System (HPS) might fail to boot from the SD card. After DDR calibration succeeds, the U-Boot Secondary Program Loader (SPL) reports:

Trying to boot from MMC1
Card did not respond to voltage select! : -110
spl: mmc init failed with error: -95 
SPL: failed to boot from all boot devices

This happens for two reasons, and both must be corrected:

• The prebuilt SPL provided with the design (src/sw/artifacts/u-boot-spl-dtb.hex) switches the SD card I/O voltage through an HPS GPIO. On the 065B MDK, the SD card voltage is switched through the I²C GPIO expander. The SPL built by the design's own Yocto flow uses the I²C GPIO expander and works.
• The HPS configuration in the design does not match the 065B MDK: HPS pins HPS_IOA_1, HPS_IOA_11, HPS_IOB_4 and HPS_IOB_5 are not configured as GPIO, and the main PLL, peripheral PLL and MPU clock overrides are enabled. With this configuration, the SD card fails to initialize even with the Yocto-built SPL.

Refer to the Agilex® 5 FPGA E-Series 065B Modular Development Kit 10GbE System Example Design user guide.

Resolution

To work around this problem in the Quartus® Prime Pro Edition Software version 26.1, follow these steps:

1. In Platform Designer, open the HPS IP (src/hw/src/ip/hps_subsys/agilex_hps.ip). In the pin mux settings, set:

• HPS_IOA_1 to GPIO0:IO0
• HPS_IOA_11 to GPIO0:IO10
• HPS_IOB_4 to GPIO1:IO3
• HPS_IOB_5 to GPIO1:IO4

2. In the same HPS IP, turn off the main PLL, peripheral PLL and MPU clock overrides.

3. Export the four HPS GPIO signals from the HPS subsystem and add the matching ports to src/hw/src/top.sv.

4. Regenerate the Platform Designer systems and compile the design (make all in src/hw/synth).

5. Build the software with the design's Yocto flow: 

cd src/sw/yocto 
. agilex5_mk_a5e065bb32aes1-ETH_1P10G-build.sh 
build_default

6. Generate the programming files with the Yocto-built SPL instead of the prebuilt src/sw/artifacts/u-boot-spl-dtb.hex:

cd src/hw/synth
quartus_pfg -c -o hps=on -o hps_path=../../sw/yocto/agilex5_mk_a5e065bb32aes1-gsrd-images/u-boot-agilex5-socdk-gsrd-atf/u-boot-spl-dtb.hex output_files/top.sof output_files/top.rbf

For QSPI boot, generate the JIC file with the same SPL: 

quartus_pfg -c output_files/top.sof output_files/top.jic -o device=MT25QU128 -o flash_loader=A5ED065BB32AE4S -o hps_path=../../sw/yocto/agilex5_mk_a5e065bb32aes1-gsrd-images/u-boot-agilex5-socdk-gsrd-atf/u-boot-spl-dtb.hex -o mode=ASX4 -o hps=1

7. Write the Yocto-built SD card image (sdimage.tar.gz) to the SD card, then program top.hps.rbf over JTAG or top.hps.jic into the QSPI flash.

This problem is scheduled to be fixed in a future release of the Agilex 5 Ethernet System Example Design for the Agilex 5 E-Series 065B Modular Development Kit.

Additional Information

• The problem was reproduced on two Agilex 5 E-Series 065B Modular Development Kit boards. The 065B Golden System Reference Design (GSRD) boots from the SD card on the same boards and SD card.
• Changing only the SPL, or only the HPS configuration, is not sufficient. With both changes, the design boots from the SD card and Linux runs normally.
• The HPS Ethernet throughput with the corrected design matches the published figure for the design (1.35 Gbit/s TCP transmit at MTU 1500).