Why does the Agilex® 5 FPGA device pin-out file list the "Direct to Factory Image" (~LOADFACTORY~) pin as an output instead of an input?

Description

Due to a data error in the published Agilex® FPGA 5 device pin-out file, the optional "Direct to Factory Image" configuration signal (signal name ~LOADFACTORY~, ball BW102, 1.8-V, SDM bank) might be listed with pin direction "output" instead of "input" for designs targeting Agilex® 5 FPGAs and SoCs because the pin-out file entry for this signal has not yet been corrected to match the signal's actual, documented behavior as an input pin used to select between the factory and application images during a remote system update.

Resolution

To work around this problem, follow these steps:

1. Do not use the device pin-out file as the authoritative reference for the "Direct to Factory Image" (~LOADFACTORY~) signal direction.
2. Refer instead to the Pin Connection Guidelines: Agilex® 5 FPGAs and SoCs (doc ID: 813266), Section 1.2.14, Secure Device Manager (SDM) Optional Signal Pins, which correctly documents this pin as an input.

Additional Information

The device pin-out file is a board-routing reference only. It is not read or enforced by the Quartus® Prime software during design compilation or fitting, so this discrepancy causes no functional failure, no compilation error, and no design-rule violation. Customers should treat the Pin Connection Guidelines handbook (doc ID: 813266) as the authoritative source whenever it disagrees with the device pin-out file.