Why does the “TCCS Report” in LVDS SERDES Intel® FPGA IP SDC report an invalid TCCS value?

Description

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 18.1 and later,  you might see the “TCCS Report” in the Timing Analyzer report an invalid value of 150 ps when using the LVDS SERDES Intel® FPGA IP with Intel® Stratix® 10 and Intel Agilex® devices.

The correct value for both device families is 330 ps.

Resolution

Check the respective device family datasheet for the correct TCCS information:

• Intel® Stratix® 10 Device Datasheet 
• Intel Agilex® Device Datasheet

This problem is fixed starting with the Intel Quartus Prime Pro Edition Software version 20.3.