Why does my Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP with 25 Gbps lanes fail timing closure when targeting an Intel® Stratix® 10 E-tile Engineering Sample (ES) device?

Description

Variants of the Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP with 25 Gbps lanes do not support Engineering Sample (ES) devices.

Resolution

To obtain the best “Quality of Result” for timing closure, launch Design Space Explorer II in the Intel® Quartus® Prime Software and perform a seed sweep.