Why does design compilation in the Quartus® Prime Pro Edition software version 25.3 and earlier fail during the fitter stage when the “Remove Redundant Logic Cells” option is enabled, and the F-Tile Dynamic Reconfiguration Suite IP is used in the design?

Description

Many users enable the “Remove Redundant Logic Cells” option to optimize their designs for area and speed. However, when this Advanced Synthesis setting (REMOVE_REDUNDANT_LOGIC_CELLS) is turned on globally for F-Tile designs  —particularly those that include the F-Tile Dynamic Reconfiguration Suite IP—  it can inadvertently remove essential support logic (QTLG-generated logic) required for proper transceiver tile operation. As a result, design compilation in the Quartus® Prime Pro Edition software version 25.3 and earlier may fail during the fitter stage with errors related to transceiver logic placement, such as: 

Error (14566): The Fitter cannot place 2 periphery component(s) due to conflicts... 
Error (175001): The Fitter cannot place 1 HSSI_PLDADAPT_TX. 

The “Remove Redundant Logic Cells” option can be enabled in two ways:

1. Through the Quartus Prime Pro Edition software GUI, as described in the Quartus Prime Pro Edition User Guide, section 1.19.1 Advanced Synthesis Settings. 
2. By adding a global assignment in the Quartus project’s QSF file:
   • set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON 

Resolution

To prevent fitter errors during compilation for F-Tile designs, it is essential to preserve the Quartus Tile Logic Generated (QTLG) support logic from being removed by the “Remove Redundant Logic Cells” optimization. This can be achieved by following these steps: 

1. Enable global redundant logic optimization for most of the design: 

• set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON 

2. Override the setting for the transceiver support logic (Tile IP) to ensure critical blocks are retained: 

• set_instance_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS OFF -to top_auto_tiles
  Note: Replace top_auto_tiles with the actual instance name used in your design. 

By selectively disabling redundant logic removal for the Tile IP, you safeguard the necessary support logic while optimizing the rest of your design, thereby avoiding fitter errors during compilation. 

This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.