Why do Quartus® Prime Pro 26.3 and earlier fail to build a Agilex® 5/Agilex® 3/Agilex® 7 FPGA M-Series VDS based design whose RTL has been generated with VDS?

Description

Due to a problem related to how VDS handles the EMIF IO96B IP (emif_io96b_hps.ip) during the RTL generation, the Quartus PRO 26.3 and earlier compilation of a Agilex® 5/Agilex® 3/Agilex® 7 FPGA M-Series design fails at Synthesis stage, when RTL is generated using VDS, with the following error:

Error(16045): Instance "u_baseline_top|u_shell_subsys|u_hps_subsys|u_emif_hps|emif_io96b_hps_inst" instantiates undefined entity "emif_io96b_hps_emif_io96b_hps_510_prw4fva"

:
Error: Failed to elaborate design: 
Error: Flow failed: Errors generated during elaboration
Error: Quartus Prime Synthesis was unsuccessful. 3 errors, 1 warning
 Error: Peak virtual memory: 2354 megabytes
 Error: Processing ended: Mon Oct 12 13:24:09 2026
 Error: Elapsed time: 00:00:27
 Error: System process ID: 2357227
Error(21794): Quartus Prime Full Compilation was unsuccessful. 5 errors, 1 warning 

Resolution

To workaround this problem, don’t use VDS to generate the RTL. If you need to modify or edit the design in VDS, save the updates and leave VDS without generating the RTL. Go back to Quartus, in the Compilation Dashboard > Compilation Flow window open the Open Settings Dialog in the IP generation section, go to Board and IP settings and in the IP regeneration policy section, select Always regenerate design files for IP cores; press Apply button and OK button. Proceed with the full design compilation.

The same can be done if you add the following setting into the corresponding .qsf file:

set_global_assignment -name PROJECT_IP_REGENERATION_POLICY ALWAYS_REGENERATE_IP

This problem will be fixed in a future release.