Why do I see hold time violations when using the 10GBASE-KR PHY Intel® Stratix® 10 FPGA IP?

Description

Due to a problem with the 10GBASE-KY PHY Intel® Stratix® 10 FPGA IP you may see minor hold time violations in the 10GBASE-KR IP during compilation.

Resolution

A possible temporary work around for this timing problem is to run seed sweeps so that better timing results are found.

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime software.