Why do I encounter timing violations in core fabric paths when running Agilex™ 7 FPGA HBM2E IP design with the core clock set close to the recommended clock frequency?

Description

Due to a problem with Quartus® Prime Pro Edition Software version 23.3, you may encounter timing violations in core fabric paths when you set the core clock close to the recommended clock frequency in the HBM2E IP designs.

 

Resolution

To workaround this issue, reduce the Fmax by 10 to 20 MHz in Quartus® Prime Pro Edition Software version 23.3 or try seed sweep with your design.