Knowledge Base Article

Why are there functional errors in hardware when using Intel® Stratix® 10 FPGA DSP blocks?

Description

Due to a problem in the Intel® Quartus® Prime Pro Edition Software versions 20.3, 20.4, and 21.1, you may see hardware failures when using the DSP blocks in Intel® Stratix® 10 devices. This problem is due to optimizations made during the Fitter Place stage while unpacking registers from the DSP block which results in functional mismatch between the expected data and the observed data.

Resolution

If you are using the Intel® Quartus® Prime Pro Edition Software version 20.3, 20.4, or 21.1, download and install the relevant patch:

For designs that have already been completed using the Intel Quartus Prime Pro Edition Software versions 20.3, 20.4, or 21.1, submit a request at the My Intel support page and reference Bug ID 14015146105.

 

This problem is fixed beginning with version 21.2 of the Intel Quartus Prime Pro Edition Software.

Updated 3 months ago
Version 2.0
critical
fpga dev tools quartus® prime software pro
stratix® 10 fpgas and socs
troubleshooting
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