Riviera* Simulation Errors of the Stratix® 10 Avalon® Streaming and Single Root I/O Virtualization (SRIOV) Interface for PCI Express* Solutions IP.

Description

Due to a problem wih the ALDEC* Riviera* simulation tool, the following or similar error will be seen when simulating the Stratix® 10 Avalon® Streaming and Single Root I/O Virtualization (SRIOV) Interface for PCI Express* Solutions IP.

ALOG: Error: VCP2950 SEG_WIDTH*2 is not a valid right-side of defparam.

Resolution

No workaround is available when using the ALDEC* Riviera* simulation tool. This problem is not seen with other supported simulators.

This problem has been reported to ALDEC*.