Intel® Stratix® 10 Device Feature Status

Description

As of November 2019, the following Intel® Stratix® 10 Device Features are planned to be supported in the future:

• Anti-Tampering
• Physically unclonable function (PUF)
• Black Key Provisioning
• Configuration and Boot from SDMMC

As of November 2019, the following Intel Stratix 10 HPS Device Features are planned to be supported in the future:

• N/A

 

 

As of November 2019, the following Intel® Stratix® 10 Device Features are supported:

• Security fuse access and dynamically elevating security
• Side channel protection
  
• eFuse AES key storage
• Bitstream Authentication (Intel® Quartus® Prime Pro Edition software version 18.1.2 and later).
• Bitstream Encryption (Intel® Quartus® Prime Pro Edition software version 19.1 and later).
• BBRAM and virtual eFuse AES Key Storage

 

 

As of November 2019, the following Intel Stratix 10 HPS Device Features are supported in specific software and tools versions:

• Secure HPS Debug Certificates
• Debug tools support for Coresight.
• Configuration Via Protocol (CVP) with HPS, using FPGA First Boot Mode.
• HPS SDRAM 2bit ECC.  
  • Bootloader release note at:   https://www.intel.com/content/www/us/en/programmable/documentation/lro1430797237133.html
  • Latest downstream branch of U-Boot:  https://github.com/altera-opensource/u-boot-socfpga/releases/tag/rel_socfpga_v2017.09_18.09.03_pr
• Linux support for SMMU features.  
  • Please see latest release notes of Linux.
  • https://patchwork.kernel.org/patch/10544563/
  • https://patchwork.kernel.org/patch/10544565/
• Warm Reset and Watchdog Warm Reset.
  • Supported in Intel® Quartus® Prime Pro Edition software version 18.1.1 build 263 (and later).
  • Support for preserving memory content through an HPS-initiated warm reset by HPS flushing L2 cache first.
  • Support for preserving memory content through a Watchdog-initiated warm reset using instructions at this KDB link.
  • An SDM I/O pin can be configured as an output to indicate that a Warm Reset has occurred.
• HPS-driven partial reconfiguration of FPGA.
  • Please see example at this link: Stratix 10 SoC Partial Reconfiguration (https://rocketboards.org/foswiki/Projects/Stratix10SocPartialReconfiguration)