How should I connect the refclk and adjpllin ports in the PLL Intel® FPGA IP when using the dedicated cascade path?

Description

There are two reference clock inputs (refclk and adjpllin) when the PLL Intel® FPGA IP is configured with the Cascade Downstream PLL option enabled. 

Resolution

You need to connect the upstream "Cascade out" signal to the adjpllin input port and you can leave the refclk input unconnected.