How do I retarget the F-Tile Ethernet Hard IP 100G example design from the Agilex® 7 FPGA I-Series Development Kit QSFP-DD J27 (QSFPDD0) to the Agilex® 7 FPGA M-Series Development Kit QSFP-DD J16 (QSFPDD CONN0)?

Description

Currently, the F-Tile Ethernet Hard IP GUI only has the option to generate the 100GE-4 example design that targets the Agilex® 7 FPGA I-Series Development Kit QSFP-DD connector J27 (QSFPDD0). There is no way for users to generate a 100GE-4 F-tile Ethernet Hard IP example design through the IP GUI that maps the IP directly to QSFP-DD connector J16 (QSFPDD CONN0) on the Agilex® 7 FPGA M-Series Development Kit (DK-DEV-AGM039EA).

For users working on the Agilex 7 FPGA M-Series devkit, this creates additional work for the users to refer to the Agilex 7 FPGA M-Series board schematics to modify the pin assignments and other SDM/Power Management settings accordingly to create an FPGA image that is compatible with the M-Series devkit.

With the steps specified below, users can now modify the devkit agnostic 100GE-4 example design to map to the Agilex 7 FPGA M-Series Development Kit’s J16 QSFP-DD connector (QSFPDD CONN0) by generating the example design using the IP GUI with Select Board set to None, then retarget the Quartus® Settings File (.qsf) pin, I/O standard, and board power-management assignments to the DK-DEV-AGM039EA J16 pinout, and then recompile to generate the FPGA image, by following the steps specified below.

Resolution

To obtain the 100GE-4 F-Tile Ethernet Hard IP example design in the Quartus® Prime Pro Edition Software that maps to Agilex 7 FPGA M-Series Development Kit (DK-DEV-AGM039EA) on J16 (QSFPDD CONN0) port, follow these steps:

1. Open the F-Tile Ethernet Hard IP Parameter Editor and set General Options as follows (see attached screenshot): PMA type FGT; Ethernet mode 100GE-4; Client interface MAC segmented; FEC mode None; PMA reference frequency 156.250000 MHz; System PLL frequency 805.664062 MHz.
   • 

      

2. Open the Example Design tab and set Select Board to None; Select device initialization clock to OSC_CLK_1_125MHZ.
   • 

      

3. Click Generate Example Design to generate the ED.
4. Edit the example design .qsf so board-level assignments match the Agilex 7 M-Series Development Kit QSFP-DD J16 (QSFPDD CONN0). Compare the originally generated .qsf (left) to the retargeted .qsf (right) in the attached screenshots. Apply pin/location, fitter/assembler power-management, and ENTITY(eth_f_hw) I/O standard / virtual-pin changes as shown in these screenshots.
   • 

      

5. Save the .qsf and run a full compile to generate the .sof.
6. Program the DK-DEV-AGM039EA board and confirm loopback link-up on J16 QSFP port by connecting the external loopback module as seen below.
   • 

      

Additional Information

• Source APS: 01009271 (Closed). Related engineering AR: QS-615224.
• RAE validated the retargeted design on DK-DEV-AGM039EA before delivering a reference QAR.