How do I reconfigure an Arria® 10 FPGA and Cyclone® 10 FPGA I/O PLL with the PLL Reconfig IP when the I/O PLL cannot be locked?

Description

PLL Reconfig IP currently checks the IO PLL lock status before it allows reconfiguration to start. This causes the mgmt_wait_request to be asserted until the IO PLL achieves lock.

Resolution

To work around this problem, edit the .v file shown below in the project IP-generated folder and change the parameter WAIT_FOR_LOCK value from 1 to 0. This will force the PLL Reconfig IP to not check the IOPLL lock status and de-assert the mgmt_waitrequest signal when the core is ready.

//synth/altera_pll_reconfig_top.v