How do I insert an LVDS buffer between an Altera_PLL and ALTLVDS_RX or ALTLVDS_TX megafunction in external PLL mode for Cyclone® V, Arria® V, and Stratix® V devices?

Description

An LVDS buffer is required to be inserted between an Altera_PLL and ALTLVDS_RX or ALTLVDS_TX mega function when used in external PLL mode for Cyclone® V, Arria® V, and Stratix® V devices when any of the following options are turned on:

Enable dynamic reconfiguration of PLL
Enable access to dynamic phase shift ports
Enable physical output clock parameters

Resolution

Download this How-To document to learn how you can add an intermediate LVDS buffer between the external PLL and ALTLVDS IP.

The How-To document references example designs which you can download in VHDL or Verilog for each of the Cyclone® V, Arria® V, and Stratix® V devices: