How can I enable external trace on the Intel® Arria® 10 SoC Development Kit?

Description

To enable external trace via MICTOR connectors J43 and J20, specific switch settings are required on the Intel® Arria® 10 SoC Development Kit.  

The Intel Arria 10 SoC Golden Hardware Reference Design (GHRD) is configured to enable 4 bit trace by default,  and can be auto-configured to enable 16 bit trace. 

Note: The MAX® V device must be removed from the JTAG chain to allow the Arm* Development Studio for Intel® SoC FPGA debugger to connect to the Intel Arria 10 FPGA Hard Processor Subsystem.

Resolution

To enable early trace (4 bit) via MICTOR connector J43
4 bit external trace via MICTOR connector (J43) is enabled in the default configuration of the Intel Arria 10 Golden Hardware Reference Design (GHRD).

Development kit settings for 4 bit trace via MICTOR conector J43:

• SW3 bits 678 must be set to on, on, on. This routes JTAG to J43.
• SW3 bit 2 must be set to on.  This takes the MAX® V device out of the JTAG chain.

To enable fast trace (16 bit) via MICTOR connector J20
The GHRD design must be re-built to enable fast trace.

1. Edit the Makefile to set HPS_ENABLE_16BIT_TRACE := 1
2. Re-build the design by running  make sof from a SoC EDS command shell.

Development kit settings for 16 bit trace via MICTOR conector J20:

• SW3 bits 6,7,8 must be set to off, on, on.  This routes JTAG to J20.
• SW3 bit 2 must be set to on.  This takes the max V out of the chain.

This problem is scheduled to be fixed in a future version of the Intel Arria 10 SoC Development Kit User Guide.