How can I edit configuration space registers 0x24 to 0x2C of Stratix® V, Arria® V, and Cyclone® V Root Port PCIe HIP?

Description

Due to a problem in the Intel® Quartus® Prime Software, the configuration registers 0x24, 0x28, and 0x2C of Root Port mode PCI Express* Hard IP (PCIe* HIP) for Stratix® V, Arria® V, and Cyclone® V devices are not writable. All 0s will be returned from these registers.
   0x24: Prefetchable Memory Base/Limit
  0x28: Prefetchable Memory Base Upper 32 Bits
  0x2C: Prefetchable Memory Limit Upper 32 Bits

Resolution

Open <Qsys file>/synthesis/<Qsys file>.v file with a text editor.
Change '.prefetchable_mem_window_addr_width_hwtcl (0)' to '.prefetchable_mem_window_addr_width_hwtcl (1)'.
Close the editor, and compile the Intel® Quartus® project.

#Note this problem is for Root Port configurations only. End Points use these register locations for BAR5, Reserved, and Subsystem Device ID/Vendor ID.

The host programs these. The user application should not try to program these registers. In End Point configurations, it is expected to read all 0s from these registers.

This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 17.1.