ERROR: iossmwr_cal_bf_cpu_cpu_test_bench/ihp_read is 'x'

Description

You may see the error message from Questasim*/Modelsim* during simulation when you instantiate the Agilex™ 7 FPGA M-Series DDR5 EMIF IP in your design.

Resolution

Workaround is to use the set USER_DEFINED_COMPILE_OPTIONS "-O0"  option to compile the design.