Does Intel provide support for Multi-port Front End IP implemented in the core FPGA fabric?

Description

Multi-port Front End logic can be used to connect multiple Avalon® bus masters to a single port Avalon slave memory controller.

Currently Altera does not provide support for soft Multi-Port Front End IP with identical functionality to the hard Multi-Port Front End IP implemented in Arria® V and Cyclone® V devices.

However, these sources of information may be useful as a starting point for users who require Multi-Port Front End functionality in the FPGA core logic :

Application Notes

AN637: Sharing External Memory Bandwidth Using the Multi-Port Front-End Reference Design (PDF)

Design files for AN 637