​​​​​​​Why do I see intermittent RX read data errors when the Agilex™ 5 MIPI D-PHY FPGA IP design example is operating at a low data rate of 150Mbps ?

Description

Due to a problem in the Quartus® Prime Pro Edition Software versions 24.1 and 24.2, you will encounter intermittent RX read data errors when testing on hardware with the Agilex™ 5 FPGA MIPI D-PHY FPGA IP design example operating at a low data rate of 150 Mbps.

Resolution

To work around this problem in the Quartus® Prime Pro Edition software version 24.2, set the Agilex™ 5 FPGA MIPI D-PHY IP GUI TX timing param “TX_HS_ZERO” to 30,  regenerate and recompile the design to ensure the change takes effect.
Currently, no workaround is available when using the Quartus® Prime Pro Edition Software version 24.1.

This problem is fixed beginning with version 24.3 of the Quartus® Prime Pro Edition Software.