SD Card Interface with DE2 in Verilog

hi evry one,

I have a similar problem.

i use Altera university program educational board De4 and i wan't to interface my board with terasic Sd_card, I first create a sopc project and complie and download *.sof into target board, then I also create a demo NiosII project "Hello world!" but when i run it as NIOS II hardware i get this error : Downloading ELF Process failed

and in console i read this

using cable "usb-blaster [usb-0]",device1,instance0x00

pausing target processor: not reponding.

resetting and trying again: failed

leaving target processor paused

can any one help me please to solve this problem

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hi evry one,

I have a similar problem.

i use Altera university program educational board De4 and i wan't to interface my board with terasic Sd_card, I first create a sopc project and complie and download *.sof into target board, then I also create a demo NiosII project "Hello world!" but when i run it as NIOS II hardware i get this error : Downloading ELF Process failed

and in console i read this

using cable "usb-blaster [usb-0]",device1,instance0x00

pausing target processor: not reponding.

resetting and trying again: failed

leaving target processor paused

can any one help me please to solve this problem

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hello there I am not able to interpret what exactly is the issue you are facing but it will be helpful if you can provide some screen shot of the console message. For your reference you can go through the video in the link below.

https://www.youtube.com/watch?v=1a_cd6fbroa

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hello there I am not able to interpret what exactly is the issue you are facing but it will be helpful if you can provide some screen shot of the console message. For your reference you can go through the video in the link below.

https://www.youtube.com/watch?v=1a_cd6fbroa

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Good morning,

to start i use this tutorial video to test my FPGA using the NIOS program.

evry thing is OK until i run the C program within the eclipse as NIOS Hardware i get this error shown in the screen shot belowhttps://alteraforum.com/forum/attachment.php?attachmentid=14115&stc=1

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it seems you have problem related to cygwin. Delete the files and try to generate the qsys component again. While generating there will be a listing in the pop up window which appears while you generate the program. In the list locate is there any error related to cygwin. If it is there then you need to update your cygwin.

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I remove the file and regenerate the HDL but nothing related to cygwin is mentionned in the popup messages.

I don't khnow what i have to do in my case :confused:

hi,

i programmer the DE4 with the IP core created by qsys tool then i used the template hello world to test the nios communication, i build with succes the project but

while runing the program as nios hardware i get this error

can any one help me to found a solution. thx