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Altera_Forum's avatar
Altera_Forum
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15 years ago

SD Card Interface with DE2 in Verilog

Hi, I am working on the DE2 development board and I have make use of an SD Card to store data (JPEG image data for the final project output). Can you kindly point me to where I should start? Ma...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

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it seems you have problem related to cygwin. Delete the files and try to generate the qsys component again. While generating there will be a listing in the pop up window which appears while you generate the program. In the list locate is there any error related to cygwin. If it is there then you need to update your cygwin.

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I remove the file and regenerate the HDL but nothing related to cygwin is mentionned in the popup messages.

I don't khnow what i have to do in my case :confused: