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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Reset and tutorial Using the SDRAM on Altera's DE0-Nano Boards

Hello,

The tutorial Using the SDRAM on Altera's DE0-Nano Boards uses the Clock Signals IP Core to provide a clock to the SDRAM.

But I found that pressing the Key(0) was not resetting.

Indeed, in altera_up_altpll.v the reset is not connected to areset of the altpll instance.

Here is a correction: 

altpll PLL_for_DE_Series_Boards (
    // Inputs
    .inclk            ({1'b0, refclk}),
    .areset            (reset),
    // Outputs
    .clk            ({3'b0, outclk2, outclk1, outclk0}),
    .locked            (locked),
);
defparam
    PLL_for_DE_Series_Boards.port_areset = "PORT_USED",

It works fine, but let me know if I overlooked something.

Thanks

1 Reply

  • rsoff's avatar
    rsoff
    Icon for New Contributor rankNew Contributor
    7 years ago

    hello,

    i am trying to work with he same tutorial.

    everything works fine except that the key(0) is not resetting.

    i tried to use your correction but still with no success.

    i noticed that in "nios_system.v" file, the reset defines as "reset_reset" and not as "reset_reset_n" as it should be:

    perhapes it might be the problem.

    what should i do to change it?

    thanks in advance.