Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Question about WM8731 - I already read the datasheet.

There is something I am not able to understand.

I'd like to record a few seconds of data from line in, store them into a ram and then playback the recorded data.

Looking at the connections provided by Altera in the schematic content, the only INPUT signal from the codec to FPGA is AUD_ADCDAT.

I got many questions:

a) Shouldn't AUD_ADCLRCK be an input signal, since it is the left/right line clock?

b) Shouldn't AUD_BCLK be an input signal (or bidir), since it is provided by the CODEC to sync the output data in master mode?

c) I was used to believe that I can assign pin directions in FPGA, so why "they" have placed only monodirectional pins in those signals, where other ones are bidir?

d) I tried to watch AUD_ADCLRCK ond AUD_BCLK connecting GPIO (using schematic ports, not in HDL) pins and wiring them to an oscilloscope (100MHz bw, so i should be able to see at least few harmonics of the pulsed signal..), but doing that the entire project does not work. I mean, it compiles, i get a programmer file but then the design does not work. On the same port I drive as output a PLL 18.4MHz signal, without the AUD_BCLK or AUD_ADCLRCK I can see it with the oscope, with another compilation with the signals internally connected, PLL signal disappears.

Anyone could explain me if I am wrong and where I am wrong?

Best regards,

L.

p.s. I am able to configure the module via I2c (using NiosII and opencores modules), so that's not a problem.

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Ok,

    I definitely missed page 50. I thought that master/slave mode was hardware selectable by grounding a pin or something similar.

    Now, I think I will use master mode to get clocks to drive a deserializer to store data into a 16bit RAM.

    I somehow -I set undriven pin as output drivin gnd instead input tristated - managed to monitor clocks wiring them to gpio, but still I am not able to view more than ONE (1!) signal in a gpio bank.

    Don't know why, it's still a "mistery".
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    I know that multiposting isn't fair in a Forum. Anyway, I would like to give a little update of the flow of my project, since I noticed that there are lots of similar threads and lots of students involeved in similar projects. Furthermore, If I am writing something wrong, I hope that someone could help or correct my believe.

    So

    --- Quote Start ---

    Now, I think I will use master mode to get clocks to drive a deserializer to store data into a 16bit RAM.

    --- Quote End ---

    the EP2C20F484C7 has something like 239,616 bits of on-chip ram. Let's ignore that in my design there are 192,384 out of 239,616 mem bits occupied ( 80 % ), even if they were all free there would have been a problem to record data from ADC.

    As soon as I am not wrong, I can configure the codec to sample from 8ks/s to 96ks/s with each sample of from 16 to 32 bits selectable.

    So, in the best situation, 8ks/s*16bit=128000bits. There's less space than required for a two seconds record available.

    I think I'll store sampled data into the flash mem.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Besides the codec datasheet, your question about suitable connection to FPGA should be basically answered by the DE1 demonstration projects, e.g. DE1_SD_Card_Audio. You'll find that the codec signals are primarly connected to the AUDIO_DAC_FIFO.v module.

    Regarding memory options for data storage, DE1 has also SRAM and SDRAM, so there should be no problem to store sound data.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    I noticed the audio fifo for the DAC; anyway, it seems that the examples configures the codec in slave mode, so the clocks are provided by the fpga.

    I'd like to try to use the master mode before "copy" their project.

    I know there are sram and sdram, but I don't have a controller (except the one in qsys) and I don't want to waste time trying to make one from scratch by myself.. so it seems that the flash controller in universitiy program is simpler to use. Any hint would be VERY appreciated!

    Question not strictly related: as I drive unused pins to tristate with low resistance, red leds are powered up but all seems to work fine (except for gpio, "obvoiously"..). If I set them as output driving ground, direct connections between adc and dac don't work.. and many led red turn on(not hex display, I know they are active low) even if they are not declared into the schematic.

    Are there any raccomandations about driving unused pins?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    I'd like to try to use the master mode before "copy" their project.

    --- Quote End ---

    Your first post gives the impression that you have difficulties to operate the codec at all. I see that this isn't the case.

    Driving pins that are connected on the board but unused in your design is a no-no in my view. They should be always set to a safe state like three-state with weak pull-up.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    Your first post gives the impression that you have difficulties to operate the codec at all. I see that this isn't the case.

    --- Quote End ---

    It was, but I figured out while working on that.

    Now my problem(s) is (are) related to store data from codec to flash, but the MAIN problem is be able to (deebug) see signals FROM codec wthout using signal tap analyzer..

    Each compilation gives differents results and I am not able do differentially understan each small change in my code. For example, a simple upcounter clocked by the AUD_BCLK when AUD_ADCLRCK is high dosen't count. I can't see nor red led increasing nor a signal with the oscope in GPIO_1[35].
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Right now, I can't exactly figure out (from the datasheet) what master out (aka from CODEC)cloks should be.

    I mean, pag. 33, left justified mode: DACLR/ADLRC is a "clock" of 1/fs. I suppose fs is the sampling rate, and I configured my device to use an 8KHz fs (sampling control register (0x10) value 0x0E).

    now, page 45:

    --- Quote Start ---

    In Master mode, DACLRC and ADCLR will be output with a 50:50 mark-space ratio with BCLK output at 64x base frequency (i.e 48Khz).. the exception again is in USB...

    --- Quote End ---

    .

    so:

    BCLK=64*8kHz=512KHz.

    BCLK=64*48kHz=3072KHz.

    NOW, with the oscope I can see the BCLK signal. And it is a 3MHz signal.

    If I set sampling rate 48Khz both for ADC and DAC (according pag. 39 registers) i don't have ANY change form the 8KHZ both for ADC and DAC sampling rate. Please, notice that the MCLK frequency required is the same, 18.432MHz.

    Other (allowed) combos in sampling rate register produces changes in output clock.

    And pelase, notice that any other change performed via software I2C is coherent, I can correctly increase volume, preamplification, analog bypass and co.

    Where am I wrong?

    I can upload the qar file, if needed.

    I tried to signal tap the system, but what i get is something strange again:

    https://www.alteraforum.com/forum/attachment.php?attachmentid=6629

    edit: just noticed that shifting the reg value from 0x0E (8 -8) to 0x02 (48 - 48) changes the DAC/ADCLRCK clock frequency.

    BUT I still am not able to understand how BCLK behaves.