Honored Contributor
Honored ContributorRight now, I can't exactly figure out (from the datasheet) what master out (aka from CODEC)cloks should be.
I mean, pag. 33, left justified mode: DACLR/ADLRC is a "clock" of 1/fs. I suppose fs is the sampling rate, and I configured my device to use an 8KHz fs (sampling control register (0x10) value 0x0E). now, page 45: --- Quote Start --- In Master mode, DACLRC and ADCLR will be output with a 50:50 mark-space ratio with BCLK output at 64x base frequency (i.e 48Khz).. the exception again is in USB... --- Quote End --- . so: BCLK=64*8kHz=512KHz. BCLK=64*48kHz=3072KHz. NOW, with the oscope I can see the BCLK signal. And it is a 3MHz signal. If I set sampling rate 48Khz both for ADC and DAC (according pag. 39 registers) i don't have ANY change form the 8KHZ both for ADC and DAC sampling rate. Please, notice that the MCLK frequency required is the same, 18.432MHz. Other (allowed) combos in sampling rate register produces changes in output clock. And pelase, notice that any other change performed via software I2C is coherent, I can correctly increase volume, preamplification, analog bypass and co. Where am I wrong? I can upload the qar file, if needed. I tried to signal tap the system, but what i get is something strange again: https://www.alteraforum.com/forum/attachment.php?attachmentid=6629 edit: just noticed that shifting the reg value from 0x0E (8 -8) to 0x02 (48 - 48) changes the DAC/ADCLRCK clock frequency. BUT I still am not able to understand how BCLK behaves.
