Altera_Forum
Honored Contributor
16 years agoProblem with Simulation
Hello ev'body, I'm trying to use Quartus II for university, I have no problems with VHDL file compilation and creation of .vwf file, but when I try to make a simulation an error appear:
can't continue timing simulation because delay information for design is missing what I should do to solve it? Could somebody help me? Thanks a lot.