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Altera_Forum's avatar
Altera_Forum
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18 years ago

Loading file from working folder

Hi guys,

I am currently using the Altera UP2 Educational Kit to perform convolution on images. I was hoping to write a program which allow my board to load a binary file (.bin) from my current working folder. The binary file contains the pixel values which i have converted from a normal JPEG picture (.jpg) using MATLAB.

I have been using the following lines:

read_from_file: process(clk)

variable indata_line: line;

variable indata: integer;

file input_data_file: text open read_mode is "c:/altera/72sp1/qdesigns/conv_3x3/noise2.bin";

begin

if rising_edge(clk) then

readline(input_data_file,indata_line);

read(indata_line,indata);

d <= conv_std_logic_vector(indata,8);

if endfile(input_data_file) then

report "end of file -- looping back to start of file";

file_close(input_data_file);

file_open(input_data_file,"c:/altera/72sp1/qdesigns/conv_3x3/noise2.bin");

end if;

end if;

end process;

However, during simulation, I faced an error reporting

"warning: invalid vector source file type specified".

"error: no valid vector source file specified and default file "c:/altera/72sp1/qdesigns/conv_3x3/conv_3x3.cvwf" does not exist"

My enquiries are:

1) What are the limitation to the vector source file type? Does text open read_mode support other file types? For example, text (.txt) or binary file (.bin)?

2) Can i use the following lines to get the processed output in my current working folder?

write_to_file: process(clk)

variable outdata_line: line;

variable outdata: integer:=0;

file output_data_file: text open write_mode is "c:/altera/72sp1/qdesigns/conv_3x3/noise2_output.bin";

begin

if rising_edge(clk) then

outdata := conv_integer(unsigned(dout));

if dv = '1' then

write(outdata_line,outdata);

writeline(output_data_file,outdata_line);

end if;

end if;

end process;

3) If not, any suggestion for me to cope with this problem? Or any references i can refer to?

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    Quartus II ignores any calls to procedures in the textio package during synthesis. Besides, how would your design read from a file when implemented on an FPGA? If you're doing a functional simulation of your design in Quartus II, the error you see occurs because you didn't create a vector waveform file to provide stimulus.

    I suggest looking at the documentation on Nios II and SOPC Builder on the Altera website. Good luck with the project.
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Hello,

    I also understand that you tried to use VHDL file I/O with Quartus simulator. Quartus simulator can be used only with vector waveform stimulus, VHDL testbenches including textio package functions are possible e. g. with ModelSim. It could be that some simulators support binary files, but the general practice is to use tabular text files, cause they are portable. If you already converted your stimulus data, you can use text files as well.

    Regards,

    Frank
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    Thanks for the advice. Any reference(s) or example(s) that i can cover to understand more about tabular text files?

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    Hello,

    I can give you an example: 

    test2:
if test=2 generate
  Process
    file IN_DAT : text open read_mode is "Omnikey.txt";
    variable LI: line;
    variable MV: integer;
	Begin
	    wait for 1 ns;
	    while not (endfile(IN_DAT)) loop
        	    wait for 10.26 ns;
        	    readline (IN_DAT, LI);
        	    read (LI, MV); 
        	    adc <= std_logic_vector(conv_signed(MV,12)) XOR X"800";
        end loop;
        file_close(IN_DAT);
        wait;	    
    End Process;
end generate;

    The data file looks like this (more lines to follow):

    -
    25
1194
1681
1096
-293
-1439
-1755

    adc is an input port for a 12 bit ad converter at the DUT. The 10.26 ns cycle isn't

    the adc sampling rate, but the corrected sampling rate of recorded test data, this

    way I present realtime test data with correct timing.

    I hope that helps,

    Frank
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    Any chances that I can store data into FPGA prior processing or I should just opt for external memory?

    If external memory is the solution, any suggested implementation on that?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    Hello,

    your question addresses three aspects:

    1. FPGA internal memory. It can generally be used up to the existing capacity wit each device. Accessing internal memory is faster and easier to achieve than any external memory.

    2. Storing data to memory. Data can either be "stored" to memory at compile time, this would be a ROM function, using hex or mif files. Or data can be stored to memory at run time. This obviously requires an interface to transport the date.

    3. Interfacing memory. FPGA internal memory can be accessed conveniently through Quartus "In-System Memory Editor" using the JTAG interface. Or through any interface mechanism realized in your code, using any existing interface, e. g. JTAG, Ethernet, RS232, custom parallel port.

    Regards,

    Frank