Issue with regenerating synthesis for IP cores in the project

Hi,

Are you adding the .qsys file or .qip in the project directory?

Thanks.

Hi,

I'm adding the .qsys file.

Thanks.

Hi,

The software will automatically regenerate the Qsys system during the compilation if you add .qsys file to the project directory. When the Intel Quartus Prime software starts the Analysis & Synthesis phase, it processes the .qsys files and generates the necessary HDL and system description files needed to compile your design.

Thanks.

Hi,

It doesn't work with .qsys file.

Thanks.

Hi,

Could you share the steps to check whether it is regenerate or not?

Thanks.

Hi,

Do you have any updates?

Thanks.

Hi,

I created Qsys Top level file with generic components.

I'm trying to update the RTL files in the path the generic component's TCL file point to.

I changed IP generation settings to "Always Regenerate design files for IP cores"

I started compilation.

Generic component file was not updated. And all the synth directory was not updated.

In short, When I have <ip_name>.ip and don't have <ip_name> synth directory of generic component IP. When running, as described above. It failed with error "<ip_name> not found"

Thanks.

Hi,

Do you mean that you are trying to modify the HDL file of the IP? If yes, you have to include the .qip file instead of .qsys file

Thanks.

Hi,

May I know if you have any updates?

Thanks.