Issue with regenerating synthesis for IP cores in the project

Hi,

I created Qsys Top level file with generic components.

I'm trying to update the RTL files in the path the generic component's TCL file point to.

I changed IP generation settings to "Always Regenerate design files for IP cores"

I started compilation.

Generic component file was not updated. And all the synth directory was not updated.

In short, When I have <ip_name>.ip and don't have <ip_name> synth directory of generic component IP. When running, as described above. It failed with error "<ip_name> not found"

Thanks.