Internal memory???

It all really depends on how much data you need to store, and the actual device on the board. (Although I know several used that dev kit, I'm not familiar with what part is on it)

You can create ram blocks of various sized with the mega function wizard. It also tells you how many resources each will take.

Usually for small packets of data, that you will store and forward you're ok, with keeping it internally. If you need to store MB's of data, you need an external ram.

Hello,

as I see, UP2 uses an oldfashion Flex10K70 FPGA (from those days, as FPGA complexity has been counted in gates yet), thus the options for using internal RAM are rather limited. Particularly, no JTAG connection to internal resources at runtime is provided, thus previously mentioned "In-System Memory Content Editor" isn't available.

However you're always able to write data to *.mif or *.hex and compile it to a ROM. Cause the UP2 board has no additional external memory, I would try this first. Another option would be to provide a parallel interface at the expansion port, where byte data can be written from PC LPT port. Cause FLEX10K has 5V supply, this would work without additional buffer hardware.

Regards,

Frank

Hello Frank,

To avoid misunderstanding, can I conclude your advices as shown below:

1) write my raw data in *.mif or *.hex format and save it in an external memory and let my FPGA read data from there and thus process it?

2) or, connect my computer's parallel port to FPGA's expansion port to allow data comunication (whether read data from or write data to my computer)?(Any reference on this?)

Thanks...

Hello,

no, I suggest to write data to *.mif or *.hex and compile it to a rom, that means the data is embedded in FPGA configuration and available from FPGA internal memory. Limitations are by FPGA memory size which is about 100 kbit with EPF10K70 and the need for recompilation to change the data.

Loading data at runtime requires an interface and some logic, at least an address counter, that stores sequential received data to consecutive memory locations, either in internal or external memory. Using a parallel interface seemes most easy to me, but I can't give a reference, perhaps other forum members can. At minimum, LPT interface needs 8 data lines and# STB. Adding ACK handshake signal (although not needed by FPGA) could ease usage of PC LPT software drivers. UART interface would be another option, but needs more overhead. Cause EPF10K70 hasn't plenty of logic resources, it may be less suitable.

Regards,

Frank