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Altera_Forum
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8 years ago

intelFPGA Monitor Program not connecting [DE1-SoC]

I'm following the tutorial on the intelFPGA monitor program for the DE1-SoC Arm 9 core, and I'm using the sample DE1-SoC Computer program with sample program JTAG Uart demonstration. However, the board will not connect using semihosting, or any other program for that matter.

Error message reads Could not query JTAG Instance IDs.Please ensure the FPGA has been configured using the correct .sof file.

It's the correct .sof file, even tried manually connecting using the GUI button to connect, still of no avail.

I tried the NIOS II program and everything runs fine.

Why can it not communicate?

It's set to the cpu0- core and not the one that powers up in reset.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    ^^Bump

    Here is the error code

    C:/altera_lite/16.0/quartus/bin64/quartus_pgm -c "DE-SoC [USB-1]" --auto

    1) DE-SoC [USB-1]

    4BA00477 SOCVHPS

    02D120DD 5CSE(BA5|MA5)/5CSTFD5D5/..

    Info: *******************************************************************

    Info: Running Quartus Prime Programmer

    Info: Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition

    Info: Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

    Info: Your use of Altera Corporation's design tools, logic functions

    Info: and other software and tools, and its AMPP partner logic

    Info: functions, and any output files from any of the foregoing

    Info: (including device programming or simulation files), and any

    Info: associated documentation or information are expressly subject

    Info: to the terms and conditions of the Altera Program License

    Info: Subscription Agreement, the Altera Quartus Prime License Agreement,

    Info: the Altera MegaCore Function License Agreement, or other

    Info: applicable license agreement, including, without limitation,

    Info: that your use is for the sole purpose of programming logic

    Info: devices manufactured by Altera and sold by Altera or its

    Info: authorized distributors. Please refer to the applicable

    Info: agreement for further details.

    Info: Processing started: Tue Sep 26 12:32:00 2017

    Info: Command: quartus_pgm -c "DE-SoC [USB-1]" -m jtag -o P;../Computer_Systems/DE1-SoC/DE1-SoC_Computer/verilog/DE1_SoC_Computer.sof@2

    Info (213045): Using programming cable "DE-SoC [USB-1]"

    Info (213011): Using programming file ../Computer_Systems/DE1-SoC/DE1-SoC_Computer/verilog/DE1_SoC_Computer.sof with checksum 0x0ADD8F95 for device 5CSEMA5F31@2

    Info (209060): Started Programmer operation at Tue Sep 26 12:32:02 2017

    Info (209016): Configuring device index 2

    Info (209017): Device 2 contains JTAG ID code 0x02D120DD

    Info (209007): Configuration succeeded -- 1 device(s) configured

    Info (209011): Successfully performed operation(s)

    Info (209061): Ended Programmer operation at Tue Sep 26 12:32:05 2017

    Info: Quartus Prime Programmer was successful. 0 errors, 0 warnings

    Info: Peak virtual memory: 284 megabytes

    Info: Processing ended: Tue Sep 26 12:32:05 2017

    Info: Elapsed time: 00:00:05

    Info: Total CPU time (on all processors): 00:00:02

    ARM_A9_HPS_arm_a9_0 will be halted upon running the preloader. Skip halting.

    ARM_A9_HPS_arm_a9_1 will be halted upon running the preloader. Skip halting.

    Halting operation timed out while halting Nios2

    Failed to halt Nios2

    Halting operation timed out while halting Nios2_2nd_Core

    Failed to halt Nios2_2nd_Core

    Info: *******************************************************************

    Info: Running Quartus Prime Programmer

    Info: Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition

    Info: Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

    Info: Your use of Altera Corporation's design tools, logic functions

    Info: and other software and tools, and its AMPP partner logic

    Info: functions, and any output files from any of the foregoing

    Info: (including device programming or simulation files), and any

    Info: associated documentation or information are expressly subject

    Info: to the terms and conditions of the Altera Program License

    Info: Subscription Agreement, the Altera Quartus Prime License Agreement,

    Info: the Altera MegaCore Function License Agreement, or other

    Info: applicable license agreement, including, without limitation,

    Info: that your use is for the sole purpose of programming logic

    Info: devices manufactured by Altera and sold by Altera or its

    Info: authorized distributors. Please refer to the applicable

    Info: agreement for further details.

    Info: Processing started: Tue Sep 26 12:32:45 2017

    Info: Command: quartus_hps --cable="DE-SoC [USB-1]" -o GDBSERVER --gdbport0=2530 --preloader=C:/altera_lite/16.0/University_Program/Monitor_Program/arm_tools/u-boot-spl.srec --preloaderaddr=0xffff13a0

    Current hardware is: DE-SoC [USB-1]

    Successfully change hardware frequency to 16Mhz

    Found HPS at device 1

    Double check JTAG chain

    HPS Device IDCODE: 0x4BA00477

    AHB Port is located at port 0

    APB Port is located at port 1

    Double check device identification ...

    >>CPU0 halted at 0x3ff82818.

    >>Resetting HPS.

    >>Downloading preloader.....

    >>Program loaded. PC set to program entry (0xFFFF0000)

    >>Setting vector base address register to: 0xffff0000

    Timed out while waiting for preloader to finish

    Preloader failed to run. HPS components may not have been configured.

    Possible causes for the failure:

    1. Linux SD card is inserted and Linux is running.

    2. FPGA-side components are accessing HPS memory.

    arm-altera-eabi-gcc -g -O1 -mfloat-abi=soft -march=armv7-a -mtune=cortex-a9 -mcpu=cortex-a9 -Wall -Wl,--defsym -Wl,arm_program_mem=0x0 -Wl,--defsym -Wl,arm_available_mem_size=0x3ffffff8 -Wl,--defsym -Wl,__cs3_stack=0x3ffffff8 -T"C:/altera_lite/16.0/University_Program/Monitor_Program/build/altera-socfpga-hosted.ld" -o "C:/Users/Owner/Documents/semihosting_example.axf" "C:/Users/Owner/Documents/semihosting_example.c"

    ELF generated at C:/Users/Owner/Documents/semihosting_example.axf.

    cd C:/Users/Owner/Documents ; arm-altera-eabi-objcopy -O srec semihosting_example.axf semihosting_example.srec

    SREC generated at C:/Users/Owner/Documents/semihosting_example.srec.

    Info: *******************************************************************

    Info: Running Quartus Prime Programmer

    Info: Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition

    Info: Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

    Info: Your use of Altera Corporation's design tools, logic functions

    Info: and other software and tools, and its AMPP partner logic

    Info: functions, and any output files from any of the foregoing

    Info: (including device programming or simulation files), and any

    Info: associated documentation or information are expressly subject

    Info: to the terms and conditions of the Altera Program License

    Info: Subscription Agreement, the Altera Quartus Prime License Agreement,

    Info: the Altera MegaCore Function License Agreement, or other

    Info: applicable license agreement, including, without limitation,

    Info: that your use is for the sole purpose of programming logic

    Info: devices manufactured by Altera and sold by Altera or its

    Info: authorized distributors. Please refer to the applicable

    Info: agreement for further details.

    Info: Processing started: Tue Sep 26 12:35:06 2017

    Info: Command: quartus_hps --cable="DE-SoC [USB-1]" -o GDBSERVER --gdbport0=2608 --preloader=C:/altera_lite/16.0/University_Program/Monitor_Program/arm_tools/u-boot-spl.srec --preloaderaddr=0xffff13a0 --source=C:/Users/Owner/Documents/semihosting_example.srec

    Current hardware is: DE-SoC [USB-1]

    Hardware frequency: 16000000

    Found HPS at device 1

    Double check JTAG chain

    HPS Device IDCODE: 0x4BA00477

    AHB Port is located at port 0

    APB Port is located at port 1

    Double check device identification ...

    Warning: Not able to halt CPU 0

    Error: DBGDSCR fails to go to expected value

    Error: Fail to write DEBUG INSTRUCTION

    Error: Fail to read CPU Register

    Error: Failed to read r15

    >>CPU0 halted at 0xfffffff8.

    >>Resetting HPS.

    Warning: Not able to halt CPU 0

    >>Downloading preloader..Error: DBGDSCR fails to go to expected value

    Error: Fail to write DEBUG INSTRUCTION

    Error: Fail to read CPU Register

    Error: Fail to write 2048 of DWORD(s) to address 0xFFFF0000 through CPU 0

    Error: Failed to write 2048 words to 0xffff0000. Loading SREC failed.

    >>Downloading user program.Error: DBGDSCR fails to go to expected value

    Error: Fail to write DEBUG INSTRUCTION

    Error: Fail to read CPU Register Stall Mode

    Error: Fail to read 1 of DWORD(s) from address 0x00000007 through CPU 0

    Error: Failed to load program.

    Error: Sticky Error: 1

    Error: Quartus Prime Programmer was unsuccessful. 0 errors, 0 warnings

    Error: Peak virtual memory: 117 megabytes

    Error: Processing ended: Tue Sep 26 12:35:21 2017

    Error: Elapsed time: 00:00:15

    Error: Total CPU time (on all processors): 00:00:03
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    I got the exactly same error, could not solve it after trying everything I can think of.

    Did you make it work eventually?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Hello,

    I am stuck with the same issue now.

    Were you able to solve this?
  • JJian21's avatar
    JJian21
    Icon for New Contributor rankNew Contributor

    Hi,

    I have the same issue, did you fix this problem?

    Btw, I cannot find the .sof file in my testing folder, where could you find it?