Hi all! :) I'm a newbie here and in FPGA trips...:rolleyes: I'm trying to make a signal delay using AND ports and I'm having some difficult... At start, I need to delay a signal ~10ns, for that and to have good accuracy, I want to make it pass for several AND ports, that I has defined like as an entity "signal_ander" and instantiated in top-level entity as a COMPONENT. I have many instances of signal_ander chained, with SA1 output as SA2 input and so over (signal ->SA1->SA2->...->SA10)... when I synthesize that, its not work properly. In Technology Map Viewer, signal_anders are not in the same order that I define in code, it is divided in several parallel blocks chained, like: signal -> SA1 ........|-> SA2 -> SA4 -> SA7 ...................|-> SA5 ->SA9 -> SA10 ........|-> SA3 -> SA6 -> SA8 How can I force Synthesizer or Fitter (I don'k know who make this) to keep the hierarchy in code? Thanks in advance and sorry my poor english... ;) # edit# I'm using Quartus II 9.1sp2 and DE20-70 board.

I already have a answer but need 4 posts to include links, sorry the spam but it's for a good cause :P

Hey guys, After many hours and some smoke out of my head, I find a solution and I let here for future reference. 1st place, I'm studying FPGA development about 1~2 months and I'm a beginner, don't believe in anything I say... :P To create signal delay with a few ns, despite what we know of discrete logic circuits, it's not a good practice use logic gates in chain. Synthesizer will try to make some optimizations and will blow up all your work. Most secure and strong (imho) way to do it is force signal route through logic cells. Delay time will be practically exact and multiple of# lcell that you use. I made this module in verilog: module pd (pulse,pulse_out); input pulse; output pulse_out; wire a, b, c, d, f, g, h, i, j, k, l; lcell lc1 (pulse,a); lcell lc2 (a,b); lcell lc3 (b,c); lcell lc4 (c,d); lcell lc5 (d,e); lcell lc6 (e,f); lcell lc7 (f,g); lcell lc8 (g,h); lcell lc9 (h,i); lcell lc10 (i,j); lcell lc11 (j,k); lcell lc12 (k,l); lcell lc13 (l,pulse_out); endmoduleand use it in top-entry entity in VHDL: ... COMPONENT pd PORT ( pulse :IN STD_LOGIC; pulse_out :OUT STD_LOGIC ); END COMPONENT; ... PA0: pd PORT MAP (A, A1); PA1: pd PORT MAP (A1, A2); PA2: pd PORT MAP (A2, A3); ... Each instance adds 4.25ns delay to signal (in DE2-70, others devices could be more or less). Technology Map in my project shows that 6 instances of "pd" are implemented using only 2 lcells, much better that using logic gates. that's the result: general schematic http://img576.imageshack.us/img576/9804/pulseshapping.png and the lcell chain :-P http://img204.imageshack.us/img204/6898/lcellchain.png Hope it will be useful to more people :)

Is the 4.25ns delay stable over the whole temperature range? Is it an average/min/max value? I'm not so sure you'll get an accurate delay with this method.

Altera_Forum

Honored Contributor

14 years ago

How to supress hierarchy optimizer for logic cells?

Hi all! :)

I'm a newbie here and in FPGA trips...:rolleyes:

I'm trying to make a signal delay using AND ports and I'm having some difficult...

At start, I need to delay a signal ~10ns, for that and to have good accuracy, I want to make it pass for several AND ports, that I has defined like as an entity "signal_ander" and instantiated in top-level entity as a COMPONENT.

I have many instances of signal_ander chained, with SA1 output as SA2 input and so over (signal ->SA1->SA2->...->SA10)...

when I synthesize that, its not work properly.

In Technology Map Viewer, signal_anders are not in the same order that I define in code, it is divided in several parallel blocks chained, like:

signal -> SA1

........|-> SA2 -> SA4 -> SA7

...................|-> SA5 ->SA9 -> SA10

........|-> SA3 -> SA6 -> SA8

How can I force Synthesizer or Fitter (I don'k know who make this) to keep the hierarchy in code?

Thanks in advance and sorry my poor english... ;)

# edit#

I'm using Quartus II 9.1sp2 and DE20-70 board.

13 Replies

Altera_Forum

Honored Contributor

13 years ago

--- Quote Start ---

Hi Jerry!

The FPGA part number used was EP2C70F896C6.

Actually, by the documentation each lcell brings about 447ps delay.

I got the 4.25ns by simulation and oscilloscope :)

I had change a lot of things meanwhile and finished it about July/2011. My last code for the pulse delay module is this:


LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY pd IS
    PORT
    (
        pulse     :in std_logic;
        pulse_d    :out std_logic
    );
end pd;
architecture beha of pd is
    
-- N gives the pulse delay multiplier. pulse_delay = N*lcell_delay
-- N must be adjusted to be coherent to pulse_delay desired and lcell_delay of using device
-- logic cell delay can be found in device performance documentation
    constant N : integer := 17;
-- lcell array with N elements
    signal delay_line: std_logic_vector(N-1 downto 0);
-- these attributes force synthesizer to keep our buffer alone :)
-- this ensures that delay is the expected
    attribute keep: boolean;
    attribute keep of delay_line: signal is true;
    
    begin
    gen_delay:
    for i IN 1  TO N-1 generate
    delay_line(i) <= delay_line(i-1);
    end generate;
    delay_line(0) <= pulse;
    pulse_d <= delay_line(N-1);
end beha;

This is easier to change, as if you need more or less delay per instance you just need to increase or decrease, respectively, the constant N value.

The delay value will be N*lcell_delay.

Hope this can be helpful :)

Cheers,

Mateus

--- Quote End ---

Dear mazzeo:

thanks for you reply, it's very useful for me.

for the lcell's delay value, where do you find from datasheet? i mean, can you point me which paper, which chapter?

Altera_Forum
Honored Contributor
13 years ago
Hi :)
Actually, it's not easy to find... :P
You can see here: ftp://ftp.altera.com/up/pub/datasheets/de2-70/cyclone_ii/cyc2_cii5v1_01.pdf

Go to page 99, Table 5–16 (LE_FF Internal Timing Microparameters) and see the last row:

tLUT 447ps for 6 speed grade (the one on DE2-70).

This parameter gives you the time between the input and output of a LUT. This is the lcell delay.

Hope this is helpful

Cheers,
Mateus
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
Hi :)
Actually, it's not easy to find... :P
You can see here: ftp://ftp.altera.com/up/pub/datasheets/de2-70/cyclone_ii/cyc2_cii5v1_01.pdf

Go to page 99, Table 5–16 (LE_FF Internal Timing Microparameters) and see the last row:

tLUT 447ps for 6 speed grade (the one on DE2-70).

This parameter gives you the time between the input and output of a LUT. This is the lcell delay.

Hope this is helpful

Cheers,
Mateus
--- Quote End ---

Thank you very much!!!
it's very useful for me!

but, it also doesn't provide the carry chain delay time,;)

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How to supress hierarchy optimizer for logic cells?

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