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Altera_Forum
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15 years ago

How to supress hierarchy optimizer for logic cells?

Hi all! :) I'm a newbie here and in FPGA trips...:rolleyes: I'm trying to make a signal delay using AND ports and I'm having some difficult... At start, I need to delay a signal ~10ns...
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Altera_Forum
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14 years ago

Hi :)

Actually, it's not easy to find... :P

You can see here: ftp://ftp.altera.com/up/pub/datasheets/de2-70/cyclone_ii/cyc2_cii5v1_01.pdf

Go to page 99, Table 5–16 (LE_FF Internal Timing Microparameters) and see the last row:

tLUT 447ps for 6 speed grade (the one on DE2-70).

This parameter gives you the time between the input and output of a LUT. This is the lcell delay.

Hope this is helpful

Cheers,

Mateus