New ContributorI'm a user of EP2C8T144C8N, a CycloneII FPGA, I trying to find suitable primitive like cycloneiii_io_ibuf for CycloneIII. I'm now trying to make a project running on CycloneII which is originally running on CycloneIII. It has a lot of LVDS primitives in the project which is suitable for CycloneIII.
Super ContributorYou can find the primitive by right-click on a new opened verilog.v file, Insert Template > Verilog HDL > Altera Primitives.
Or you can refer to the document "Designing with Low-Level Primitives"
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_low_level.pdf
You may checkout this webpage for supported buffer primitives.
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
Please be informed that there will be delay in response in the following week due to holiday season.
Super ContributorWishing you a Happy New Year 2023!
As we do not receive any response from you on the previous question/reply/answer that we have provided. I now transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
Thank you.
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
