Forum Discussion
RichardT_altera
Super Contributor
3 years agoYou can find the primitive by right-click on a new opened verilog.v file, Insert Template > Verilog HDL > Altera Primitives.
Or you can refer to the document "Designing with Low-Level Primitives"
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_low_level.pdf
You may checkout this webpage for supported buffer primitives.
Best Regards,
Richard Tan
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