How to create echo delay in audio

Hello, im working on a project that needs to reproduce an audio signal using the the DE2 board. I need to create several effect for the final output, and one of them is the delay of the input signal causing echo. I im basing my project on the DE2_i2csound example.

The signal im working on is called RIGHTDATA and LEFTDATA, they already

have the volume adjusted.

The problem is that i dont get any echo after the sum of the original signal and the delay one.

I dont know if that is the right place to save the delayed signals.

Thankyou for your time...

MAQUINA: PROCESS (CLK,LR,BCLK,COUNTER_L,COUNTER_R)

BEGIN

if (rising_edge(CLK)) then

CC1<=CC0;

CC0<=BCLK;

if ((C1='0') and (C0='1')) then

if (LR='0') then

case (COUNTER_R) IS

when 0=> RIN(15)<=ADC;

DAC<=ROUT(15);

when 1=> RIN(14)<=ADC;

DAC<=ROUT(14);

when 2=> RIN(13)<=ADC;

DAC<=ROUT(13);

when 3=> RIN(12)<=ADC;

DAC<=ROUT(12);

when 4=> RIN(11)<=ADC;

DAC<=ROUT(11);

when 5=> RIN(10)<=ADC;

DAC<=ROUT(10);

when 6=> RIN(9)<=ADC;

DAC<=ROUT(9);

when 7=> RIN(8)<=ADC;

DAC<=ROUT(8);

when 8=> RIN(7)<=ADC;

DAC<=ROUT(7);

when 9 => RIN(6)<=ADC;

DAC<=ROUT(6);

when 10=> RIN(5)<=ADC;

DAC<=ROUT(5);

when 11=> RIN(4)<=ADC;

DAC<=ROUT(4);

when 12=> RIN(3)<=ADC;

DAC<=ROUT(3);

when 13=> RIN(2)<=ADC;

DAC<=ROUT(2);

when 14=> RIN(1)<=ADC;

DAC<=ROUT(1);

when 15=> RIN(0)<=ADC;

DAC<=ROUT(0);

when 16=>

if (MUTE='1') then

--ROUT<=RIN;

ROUT(15 downto 0)<=RAM_R(9)+RIGHTDATA(19 DOWNTO 4);

RAM_R(9)<=RAM_R(8);

RAM_R(8)<=RAM_R(7);

RAM_R(7)<=RAM_R(6);

RAM_R(6)<=RAM_R(5);

RAM_R(5)<=RAM_R(4);

RAM_R(4)<=RAM_R(3);

RAM_R(3)<=RAM_R(2);

RAM_R(2)<=RAM_R(1);

RAM_R(1)<=RAM_R(0);

RAM_R(0)<=RIGHTDATA(19 DOWNTO 4);

else

ROUT<= (others=>'0');

end if;

when others=>

DAC<='0';

end case;

else

case (COUNTER_L) IS

when 0=> LIN(15)<=ADC;

DAC<=LOUT(15);

when 1=> LIN(14)<=ADC;

DAC<=LOUT(14);

when 2=> LIN(13)<=ADC;

DAC<=LOUT(13);

when 3=> LIN(12)<=ADC;

DAC<=LOUT(12);

when 4=> LIN(11)<=ADC;

DAC<=LOUT(11);

when 5=> LIN(10)<=ADC;

DAC<=LOUT(10);

when 6=> LIN(9)<=ADC;

DAC<=LOUT(9);

when 7=> LIN(8)<=ADC;

DAC<=LOUT(8);

when 8=> LIN(7)<=ADC;

DAC<=LOUT(7);

when 9=> LIN(6)<=ADC;

DAC<=LOUT(6);

when 10=> LIN(5)<=ADC;

DAC<=LOUT(5);

when 11=> LIN(4)<=ADC;

DAC<=LOUT(4);

when 12=> LIN(3)<=ADC;

DAC<=LOUT(3);

when 13=> LIN(2)<=ADC;

DAC<=LOUT(2);

when 14=> LIN(1)<=ADC;

DAC<=LOUT(1);

when 15=> LIN(0)<=ADC;

DAC<=LOUT(0);

when 16=>

if (MUTE='1') then

LOUT(15 downto 0)<=RAM_L(9)+LEFTDATA(19 DOWNTO 4);

RAM_L(9)<=RAM_L(8);

RAM_L(8)<=RAM_L(7);

RAM_L(7)<=RAM_L(6);

RAM_L(6)<=RAM_L(5);

RAM_L(5)<=RAM_L(4);

RAM_L(4)<=RAM_L(3);

RAM_L(3)<=RAM_L(2);

RAM_L(2)<=RAM_L(1);

RAM_L(1)<=RAM_L(0);

RAM_L(0)<=LEFTDATA(19 DOWNTO 4);

else

LOUT<= (others=>'0');

end if;

when others=>

DAC<='0';

end case;

end if;

end if;

end if;

END PROCESS MAQUINA;