Forum Discussion
Altera_Forum
Honored Contributor
17 years agoAs a first remark, without signal and type definition, your code isn't understandable. I'm not motivated to guess about possible data definitions. Also the ADC and DAC data processing isn't clear, but it's not directly related to your question. I simply assume, that you are able to interface the audio codec correctly.
Echo usually implies a delay above 100 ms, respectively a few thousand samples, but may range up to many seconds. This can be done with RAM ring buffer, addressed by write and read pointers. The read pointer offset defines the delay. However, FPGA internal RAM is only sufficient for very small delays, external RAM would be better suited.