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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Flash Memory and SRAM data pin assignment

Hi,

I'm having problem in assigning pins in using flash memory and SRAM. In my sopc, I'm using one avalon mm tristate bridge to link to the SRAM and Flash. Im not sure where should I assign the data pins for flash memory. The details of SRAM and flash are

SRAM: 256K x 16bit

Flash: 4M x 8 bit

Once I generated the processor and updated it in bdf in quartus, the output from the processor are:

address_to_the_cfi_flash[21..0]

chip_select_to_the_static_ram_0[21..0]

read_n_to_the_cfi_flash

read_n_to_the_static_ram_0

select_n_to_the_cfi_flash

tristate_bridge_address[17..0]

tristate_bridge_byteenablen[1..0]

tristate_bridge_data[15..0]

write_n_to_the_cfi_flash

write_n_to_the_static_ram_0

where should I assign the data pins for flash memory and SRAM?

Thanks

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Lower 8 bits of tristate_bridge_data to both devices, upper 8 only to the SRAM. Be sure to connect the byteenable signal to the SRAM, as well.

    Cheers,

    - Ura
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    I'm having the same problem with Cyclone III Development Kit. Using 2 tri-state bridges connected to a SSRAM and FLASH.

    I would certainly need a step-by-step guide to do this. I've been fiddling with this for some time now :mad:

    Do I specify the shared pins in the Pin Planner?

    Thanks in advance!