Error while using Simulation Waveform Editor

Thank you that issue is resolved.

Now I'm facing a new problem. I get an error saying :

Error (suppressible): (vsim-3601) Iteration limit 5000 reached at time 25 ns.

I am trying to simulate a simple RS Latch. My code is below and I have attached the screenshot of the error as well. I tried searching how to resolve this error. I read this can occur when there is an infinite loop, but I'm not sure how my code can end up in such a loop. Am I doing something wrong? I'm kinda new to Quartus as well

 

module part1(clk, R, S, Q);

	input clk, R, S;
	output Q;
	
	wire R_g, S_g, Qa, Qb /* synthesis keep */;
	
	and(R_g, R, clk);
	and(S_g, S, clk);
	nor(Qa, R_g, Qb);
	nor(Qb, S_g, Qa);
	
	assign Q = Qa;
	
endmodule