DE2 SDRAM Image Processing

Question

Hi, I am attempting to perform some image processing on the DE2 board, using the TRDB-DC2 camera module, the on board SDRAM and the VGA output. The processing that i need to do means that there must be multiple writes to memory before being output to the VGA. I am trying to use the given SDRAM controller for the example camera project, which acts as a frame buffer.

I need help with actually getting the stored image data out of the SDRAM allowing for the VGA to simultaneously have access when needed. Also I need to have access to specific addresses, and not just putting in a beginning and end address and have it read row by row. Can this be done by editing the existing controller, and if so how?

Any help would be greatly received

Thanks

altera_forum · Answer

Which SDRAM controller do you mean - sdram_0.v? If so, I don't exactly understand what's the problem in "having access to specific addresses". The sdram controller generally allows access to specific addresses. A more complicated problem is in arbitrating the different read and write requests, because SDRAM has a latency and consumes additional time when changing the active row. FIFOs may be necessary to perform e. g. the VGA output read accesses in bursts, reducing the addressing overhead.

altera_forum · Answer

I'm using Sdram_Control_4Port is the one I am using, and it has all the fifos etc for reading and writing, its just that instead of taking in an address, it takes in a starting address and max address for each port, and I assume that it just automatically increments accordingly when it needs to. Obviously I am concerned about reading more than the writing as the VGA is constantly reading and I need to do my processing simultaneously.

altera_forum · Answer

I wasn't aware of the 4-port component. It should basically have the required functionality, if not, it could be extended. I would expect, that it's also capable of single word accesses.

altera_forum · Answer

As a supplement, it could be of course that the intended amount of R/W accesses exceeds the RAM interface's throughput. I also don't know, if the said 4-port component has optimzed timing when scheduling accesses from the ports.

altera_forum · Answer

Hallo Warren.

I do my project whith DE2 board and TRDB-DC2 too.

I don't success to communicate with the camera,I sink that a problem is whith pins assignment.

I'll appreciate,if you could send me a pin assignment file.

Thank you,

Roman

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DE2 SDRAM Image Processing

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