DE2 SDRAM Image Processing

Which SDRAM controller do you mean - sdram_0.v? If so, I don't exactly understand what's the problem in "having access to specific addresses". The sdram controller generally allows access to specific addresses. A more complicated problem is in arbitrating the different read and write requests, because SDRAM has a latency and consumes additional time when changing the active row. FIFOs may be necessary to perform e. g. the VGA output read accesses in bursts, reducing the addressing overhead.