Yeah, im having this problem with numerous designs.
Library ieee;
Use ieee.std_logic_1164.all;
Entity trafficlights is
Port (SenA, SenB, Clk, Init: in bit;
Lights: out bit_vector (5 downto 0));
End trafficlights;
Architecture moore of trafficlights is
Type state_type is (S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11);
Signal state: state_type;
Begin
Process (Clk, Init)
begin
if Init ='1' then state <= S0;
elsif Clk= '1' and clk'event then
case state is
when S0=> if SenA ='0' and SenB ='0' then state<=S1;
elsif SenA ='0' and SenB ='1' then state<=S4;
elsif SenA ='1' and SenB ='0' then state<=S0;
elsif SenA ='1' and SenB ='1' then state<=S1;
end if;
when S1=> if SenA ='0' and SenB ='0' then state<=S2;
elsif SenA ='0' and SenB ='1' then state<=S2;
elsif SenA ='1' and SenB ='0' then state<=S2;
elsif SenA ='1' and SenB ='1' then state<=S2;
end if;
when S2=> if SenA ='0' and SenB ='0' then state<=S3;
elsif SenA ='0' and SenB ='1' then state<=S3;
elsif SenA ='1' and SenB ='0' then state<=S3;
elsif SenA ='1' and SenB ='1' then state<=S3;
end if;
when S3=> if SenA ='0' and SenB ='0' then state<=S4;
elsif SenA ='0' and SenB ='1' then state<=S4;
elsif SenA ='1' and SenB ='0' then state<=S4;
elsif SenA ='1' and SenB ='1' then state<=S4;
end if;
when S4=> if SenA ='0' and SenB ='0' then state<=S5;
elsif SenA ='0' and SenB ='1' then state<=S5;
elsif SenA ='1' and SenB ='0' then state<=S5;
elsif SenA ='1' and SenB ='1' then state<=S5;
end if;
when S5=> if SenA ='0' and SenB ='0' then state<=S6;
elsif SenA ='0' and SenB ='1' then state<=S6;
elsif SenA ='1' and SenB ='0' then state<=S6;
elsif SenA ='1' and SenB ='1' then state<=S6;
end if;
when S6=> if SenA ='0' and SenB ='0' then state<=S7;
elsif SenA ='0' and SenB ='1' then state<=S6;
elsif SenA ='1' and SenB ='0' then state<=S10;
elsif SenA ='1' and SenB ='1' then state<=S7;
end if;
when S7=> if SenA ='0' and SenB ='0' then state<=S8;
elsif SenA ='0' and SenB ='1' then state<=S8;
elsif SenA ='1' and SenB ='0' then state<=S8;
elsif SenA ='1' and SenB ='1' then state<=S8;
end if;
when S8=> if SenA ='0' and SenB ='0' then state<=S9;
elsif SenA ='0' and SenB ='1' then state<=S9;
elsif SenA ='1' and SenB ='0' then state<=S9;
elsif SenA ='1' and SenB ='1' then state<=S9;
end if;
when S9=> if SenA ='0' and SenB ='0' then state<=S10;
elsif SenA ='0' and SenB ='1' then state<=S10;
elsif SenA ='1' and SenB ='0' then state<=S10;
elsif SenA ='1' and SenB ='1' then state<=S10;
end if;
when S10=> if SenA ='0' and SenB ='0' then state<=S11;
elsif SenA ='0' and SenB ='1' then state<=S11;
elsif SenA ='1' and SenB ='0' then state<=S11;
elsif SenA ='1' and SenB ='1' then state<=S11;
end if;
when S11=> if SenA ='0' and SenB ='0' then state<=S0;
elsif SenA ='0' and SenB ='1' then state<=S0;
elsif SenA ='1' and SenB ='0' then state<=S0;
elsif SenA ='1' and SenB ='1' then state<=S0;
end if;
end case;
end if;
end process;
Process (state)
Begin
Case state is
When S0 => (Lights) <= "001100";
When S1 => (Lights) <= "001100";
When S2 => (Lights) <= "001100";
When S3 => (Lights) <= "001100";
When S4 => (Lights) <= "001100";
When S5 => (Lights) <= "010100";
When S6 => (Lights) <= "100001";
When S7 => (Lights) <= "100001";
When S8 => (Lights) <= "100001";
When S9 => (Lights) <= "100001";
When S10 => (Lights) <= "100001";
When S11 => (Lights) <= "100010";
end case;
end process;
end Moore;