.sof file not being created

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Hi,

After simulating my verilog file, .sof file is not being generated by default in order for me to program my file to the de1 board. I'm unsure why it's not producing these files.

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Maybe you don´t have a license file.

Look in the compilation report and search for "license". See what you find. Also, see if you are getting a "<design_name>_time_limited.sof" file.

Jake