u-boot and FPGA to HPS SDRAM bridge, removed reset bridge in source code

Hi,

May I know which device you are working on? For Example in Cyclone V, we can enable the bridge via a uboot script using run bridge enable handoff in uboot.

I noticed you posted the same question on another post. Can we followup on one post instead?

Thanks.

Hello,

it is an cyclone v.

no i didnt post the same question twice times.

greetings

Hi,

I apologize, were you using the latest version of Quartus and SoC EDS? For Cyclone V SoC it should be the 18.1 std.

May I know how did you generate your preloader and u-boot?

Hello,

yes we use the latest quartus software.

u-boot were from gitlab denx source, but i test although the altera source code.

same issue

but the main question is:

why is the reset removed from the source, i checked the altera source and there is the reset although removed.

with the new source code the sdram bridge is not working after power on.

plz check my links at the first post.

thanks

I apologize if i missed anything, when you mentioned using altera source code, which uboot version are you working on if you may share?

Hello,

we use the uboot 2020.01 and patch the source code.

Hi,

Thanks for the info, have you try running "run bridge_enable_handoff" in the Uboot command prompt? For Cyclone V SoC, this command need to be entered, or put in a Uboot script to enable all the bridges.

Also, have you tested to run our GHRD image with our guide flow to see if everything works fine using our image?:

https://rocketboards.org/foswiki/Documentation/GSRDBootLinuxSd