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CJere3's avatar
CJere3
Icon for New Contributor rankNew Contributor
7 years ago

Timing requirement about Avalon-ST in triple speed ethernt IP core

in TSE datasheet,the timing requirement about the data using by Avalon-ST interface.but the figure 51 and 55(shown below) confuse me.in Avalon-ST transmit interface as shown in figure 55,when should ...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

HI,

The TX timing diagram may not draw it nicely but in general data is changing on rising clock edge.

Thanks.

Regards,

dlim