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jjac705
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3 years ago

SoC EDS issue

Hi, I attempted the SoC EDS as per the pdf SoC_software_lab_16.0.pdf on rocketboards.org. I was asked to see the link to create a u-boot-socfpga. In that, it was told to clone a github file which ...
jjac705's avatar
jjac705
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3 years ago

Hi Aik Eu,

Actually I have some VHDL codes where my output was 32 bits. I have done the software simulation on ModelSim. I was suggested by one of my peer that HPS can be used to display the outputs for the same. Hence, I embarked on doing the same.

I attempted to use the same VHDL codes on Quartus using the Signaltap logic analyzer and it seems like the samples are not enough. It seems I need to turn back to HPS again.

Hope you understood my plight.

Thanking You

Yours Sincerely

Jerry Jacob